Field effect transistors (FETS) are widely used today. A common variety are often referred to as metal-oxide-semiconductor (MOS) devices even though the “metal” may be made of other things than simple metals and the “oxide” may also be of other things than simple oxides. Accordingly, as used herein the terms “metal” and “oxide” are intended to include any convenient and stable conductive and insulating materials, respectively. A particular variety of MOS devices useful for power applications are TMOS devices, so called because the current pathway follows a “T” shape.
FIG. 1 illustrates prior art super-junction TMOS device 20. TMOS device 20 is formed in and on substrate 21 having N+ drain region 22 of, for example, 0.01 Ohm-cm resistivity and with thickness Ddrain of about 350 micrometers thickness, and with its lower surface coupled to drain contact 23. N-Epi region 24 lies above drain region 22 and has thickness Depi typically about 30-50 micrometers. P-body regions 26 extend distance Dbody about 1-3 micrometers into N-Epi region 24 from upper surface 25 of substrate 21. P+ body contact regions 28 and N+ source regions 30 extend into P− body regions 26 from upper surface 25. N+ source regions 30 have thickness Ds typically about 0.3 micrometers. Gate insulator 32 covered by gate 34 extends between source regions 30 over channel regions 27 in P-body regions 26 and inter-body region 36 located between P-body regions 26. Contact 31 is provided to P+ body contact regions 28 and N+ source regions 30, and connection 35 is provided to gate 34. Beneath P-body regions 26 and extending through N-epi region 24 to drain 22 are P-partition regions 38 of lateral width LP. Beneath inter-body N regions 36 are N-drift regions 39 of depth Ddrift and of lateral width LN extending through N-epi region 24 to drain 22. LP and LN are typically about 5-8 micrometers. P-partition regions 38 and N-drift regions 39 form a set of substantially equal width vertical channels extending distance Ddrift from P body regions 26 and inter-body regions 36, respectively, through N-epi layer 24 to N+ drain contact 22, generally a distance of about Ddrift=32-48 micrometers. To obtain superjunction action with prior art device 20, the quantities of impurities in N-drift regions 39 should be within 100% to 150% of the quantity of impurities in P-partition regions 38. When the appropriate bias is applied, current flows from sources 30 to drain 22 as shown by arrows 37. WG is the gate length and Lacc is the length between facing P-body regions 26. Thus, the channel lengths LCH are approximately (½)*(WG−Lacc). In the prior art, WG is typically of the order of about four micrometers or more and Lacc about 2.4 micrometers or more.
While conventional TMOS devices are very useful, they suffer from a number of limitations well known in the art. For example, the on-resistance RDS(ON) is often higher than desired, the gate-source and gate-drain capacitances CGS and CGD are often larger than desired, the gate charge QG can be larger than desired, and other device properties may also be less than optimum. While various improvements have been made in the past to attempt to ameliorate these and other problems, such as employing superjunction structures (see for example, U.S. Pat. No. 6,291,856 B1 to Yasushi Miyasaka et al), it has often been the case that what is done to improve one characteristic results in degradation of another important characteristic or substantially increased manufacturing difficulty. For example, while RDS(ON) can be improved by increasing the doping in epi-region 24, this tends to undesirably increase CGD and/or QG, and/or undesirably reduce the break-down voltage BVDSS. Conversely, while CGD and QG can be reduced by thickening the gate oxide above region 36 this tends to increase RDS(ON) and/or undesirably perturb the threshold voltage. While use of a superjunction structure like that shown in FIG. 1 may avoid some of these complications by forming charge balanced drift region 38, 39, it is difficult and expensive to fabricate the required side-by-side arrangement of P and N closely packed parallelepipeds 38, 39 whose heights (Ddrift) are generally 4-5 times their width (LP, LN), such as is illustrated in FIG. 1. For higher frequency operation when lateral device dimensions (e.g., WG, LP, LN, etc.) generally must be made smaller, this is even more difficult to accomplish since smaller values of LP and LN are often associated with larger values of Ddrift. The greater the aspect ratio (e.g., LN/Ddrift) the more difficult and expensive it is to fabricate the devices, especially larger area devices also adapted to handle higher currents. These and other factors combine to limit the ability of conventional devices to switch large amounts of power at higher speeds. Thus, there is an ongoing need for MOS devices whose structure and mode of manufacture avoids these and other difficulties. Accordingly, it is desirable to provide MOS devices having both higher current and higher switching speeds. In addition, it is desirable the changes in device structure and method of fabrication used to improve the devices be compatible with existing device manufacturing techniques, especially with planar technology. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.